Synchronous Counter : Phased Logic Example

A description of the schematic is given below.

• The inputs to the counter are :
  
  • CLK : The global clock signal
  • CE : Count Enable. When CE = '1' the counter increments by one.
  • R_B : Reset. This signal is active low.
    
• The three outputs of the schematic are :
  
  • D0 : The least significant bit of the output.
  • D1 : The most significant bit of the output.
  • TC : Terminal Count goes high when both D0 and D1 are high.
    
• The components of the schematic are :
  
  • G1, G4 AND G5 are two input AND gates. The component used is AND201
  • G2 and G3 are two input XOR gates. The component used is XOR201
  • G6 is a three input AND gate. The component used is AND301
  • D1 and D2 are D-Flip Flops. The component used is DFRF301
    
• The two-bit counter counts from B"00" to B"11" on the rising-edge of the clock with the CE signal high.
  
• When the R_B signal goes low, all the values are reset to '0'. This is asserted to initialize the counter.
  
• When both data outputs are high, the TC signal is asserted high. This indicates the end of the count sequence. In the next cycle, the counter rolls back to B"00".
  

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