Phased Logic Counter : Phased Logic Example

A description of the schematic is given below.

• The components of the schematic are :
  
  • G1, G4 AND G5 are phased logic two input AND gates. The component used is PL_AND201
    
  • G2 and G3 are phased logic two input XOR gates. The component used is PL_XOR201
    
  • G6 is a phased logic three input AND gate. The component used is PL_AND301
    
  • D1 and D2 are replaced by the phased logic buffer gate which is the equivalent of a flip-flop of a synchronous design. They are now renamed as D1BUF and D2BUF. The component used is PL_BUFF101
    
  • The above detailed components are the exact equivalent components of the synchronous library. However this does not complete the conversion from synchronous design to phased logic design. The additional components used are listed below.
    
  • The circuit is to be closed in nature. In order to achieve the same, input and output buffers are used to connect them together. There should exist a separate buffer for each input or output. In this example, INBUF1 and INBUF2 are used for two inputs and OUTBUF is the buffer for the TC output. The component used is PL_BUFF101
    
  • A test gate or an interface gate is inserted between the output and input buffers to interact with the outside world. In this case, a test gate is used. The test gate uses all the outputs as its inputs and triggers when all the inputs have valid data on them. When it triggers, a new test vector is put on its outputs which inturn are the new inputs to the circuit. In this example, we see that the buffers D1BUF and D2BUF behave as output buffers as well. Hence we did not use specific output buffers for the Q1 and Q0 outputs.
    
  • The Q1_LATCH, Q0_LATCH and the TC_LATCH are synchronous components used to latch the data for a complete simulation cycle. They are used for simulation purposes only. The component used is DFRF301
    

Observations...

• The conversion to phased logic is not without its drawbacks. There is an increase in the number of signals due to LEDR encoding. LEDR uses two signals to encode value and timing for a controlled logic signal. By transmitting the timing information with the value of a signal, the circuit becomes delay-insensitive.
  
• The phased logic design, up to now, is said to be live but not safe. This means that each signal in the design has at least one token on it. This does not guarantee correct circuit operation though. Multiple tokens on a signal without careful precautions will cause the circuit to operate incorrectly. In order to make the circuit safe, feedback is added with other considerations made for multiple-token signals. This is detailed fully in Dr. Dan Linder's work. The schematic with its initial token marking is as shown in this figure.
  

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