Phased Logic Tutorial

Index

1. Introduction
2. Making up a Synchronous Design
3. Conversion of the Synchronous Design to an Equivalent Phased Logic Design
4. Making the Phased Logic Design safe

Introduction

This tutorial assumes a basic conceptual understanding of phased logic by the reader. An overview of phased logic is given in Dr. Dan Linder's paper. His approach supports the synchronous logic paradigm which makes it easier to shift from synchronous logic to delay insensitive circuitry.

Synchronous Design

• A schematic is developed using the synchronous cells in the library. This is the starting point in converting the synchronous logic to phased logic circuitry.
  
• The schematic, for this example, is shown.
  
• Next, the schematic is converted to its phased logic equivalent.
  

Equivalent Phased Logic Design

• Each synchronous gate present in the schematic is replaced by its equivalent phased logic gate.
  
• Each flip-flop is replaced by its equivalent phased logic component, the buffer. The clock connections are then eliminated.
  
• The circuit is then isolated or closed due to the absence of a clock. Buffers are inserted at the inputs and outputs. An interface gate or a test gate is used between the input and output buffers as a connection with the external world.
  
• The equivalent circuit is as shown here.
  

A Safe Phased Logic Design

• Feedback paths are added to a LIVE phased logic design to make it SAFE. A feedback path is used so all nets in the design will be in a loop with only one token marking.
• In some designs, there could be more than one feedback path feeding into a single component. For these situations a C-element is used to connect the feedback paths to the component.
• A SAFE Phased Logic Design is shown
• A simulation of the two bit counter.