Publications

• Early Evaluation for Phased Logic Circuits Using BDDs and MVL, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 24-26, 2005, pp. 400-403.

• R. Reese, M. Thornton, and C. Traver, "A Coarse-Grain Phased Logic CPU", IEEE Transactions on Computer, Vol 54, No. 7, July 2005, pp 788-799.

• R. Reese, M. Thornton, C. Traver, and D. Hemmendinger, "Early Evaluation for Performance Enhancement in Phased Logic", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol.24, No.4, April 2005, pp. 532-550.

• R. Reese, M. Thornton and C. Traver, "Fast two-phase micropipeline control wrapper for standard cell implementation", Electronics Letters ,Volume: 40 , Issue: 4 , Feb 2004, Pages:227 - 229.

• R. Reese, M. Thornton and C. Traver, "Two-phase micropipeline control wrapper with early evaluation", Electronics Letters ,Volume: 40 , Issue: 6 , March 2004, Pages:365 - 366.

• R. Reese, M. Thornton and C. Traver, "A Coarse-grained Phased Logic CPU", Ninth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), Vancouver, BC, Canada, May 2003, pp 2-13.

• K. Fazel, M. Thornton and R. Reese, "PLFire: A Visualization Tool for Asynchronous Phased Logic Designs", IEEE/ACM Conf. On Design, Automation and Test in Europe (DATE), March 2003,pp 1096-1097.

• R. Reese, M. Thornton and C. Traver, "A Fine-grained Phased Logic CPU", IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), Tampa, Florida, February, 2003, pp 70-79.

• R.B. Reese, S. Sikandar-Gani, "Control versus Compute Power within a LEDR-style Self-timed Multiplier", Proc. of the IEEE Symposium on Circuits and Systems, Tulsa, OK, August 2002, pp 302-305.
  

• M.A. Thornton, K. Fazel, R.B. Reese, C. Traver, "Genereralized Early Evaluation in Self-Timed Circuits", DATE 2002, Paris, France, March 4-8, 2002, pp 255-259.
  

• R. B. Reese, M.A. Thornton, C. Traver, "Arithmethic Logic Circuits using Self-Timed Bit Level Dataflow and Early Evaluation", Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Austin, Texas, 23-26, September 2001, pp. 18-23.
  

• C. Traver, R. B. Reese, M.A. Thornton, "Cell Designs for Self-Timed FPGAs", Proceedings of the 14th Annual IEEE International ASIC/SOC Conference, September 2001, pp 175-179.
  

• R. B. Reese, M.A. Thornton, C. Traver, "Arithmethic Logic Circuits using Self-Timed Bit Level Dataflow and Early Evaluation", presented at IWLS 2001, June 2001.
  

• Robert B. Reese, Traver C., "Power Considerations in Phased Logic Gate Design", Technical Report MSSU-COE-ERC-01-03 ( PDF).

• Robert B. Reese, Traver C., "Synthesis and Simulation of Phased Logic Systems", presented at IWLS 2000, Technical Report MSSU-COE-ERC-00-09 ( PDF).

• Daniel H. Linder and James C. Harden, "Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry," IEEE Transactions on Computers, vol. 45, pp. 1031-1044, Sept. 1996.

• Daniel H. Linder, Phased Logic: A Design Methodology for Delay-Insensitive, Synchronous Circuitry. Ph.D. dissertation, Mississippi State University, 1994.

• ASYNC '2003 presentation
• ZIP archive of ISVLSI '2003 presentation
• Recent Phased Logic Overview - this zip archive contains Powerpoint and flash animations for a brief summary of our most important results, including new work on halting token flow in PL netlist to improve performance and reduce power.

• ICCD 2001 presentation , this zip archive contains the Powerpoint and Flash animations for the ICCD 2001 paper.

Contracts

Current funding is provided by the NSF, Award #0098272 , Self-Timed FPGA Systems