This work was made possible through a generous grant from Dallas Semiconductor

Introduction

Goal:

The goal of this project is to create a standard cell design flow which will produce a fully placed-and-routed layout from a given VHDL model, submittable to MOSIS for fabrication.

Task Outline:

	Imported a basic standard cell library from a generic technology to the North Carolina State University Cadence Design Kit (NCSU CDK) AMI 0.5 micron technology. Original basic standard cell library was created by Scott Jennings (a former MSU student).
	Imported the Tanner Hi-ESD Pad Library from the MOSIS website (click here for source).
	Generated abstracts of standard cells and I/O pads using Cadence Abstract Generator, in LEF format.
	Investigated Place-and-Route techniques using Cadence Design Planner and Silicon Ensemble.
	Designed a VHDL model of a DS1620 temperature sensor interface. Put VHDL model through standard cell design flow, to obtain a standard cell implementation of the design.
	Submitted design to MOSIS for fabrication.

ICFB Layout View of Temperature Sensor Interface