This work was made possible through a generous grant from Dallas Semiconductor

Downloads

Please read disclaimer before downloading and using any of the files in this section.

Standard Cell Files

Tar file containing standard cell library  (9.65 Mb) This is an ICFB database library that contains: 
  1.     Basic standard cells, created by Scott Jennings and modified by Wei Lii Tan. 
  2.     ESD Protection I/O pads from the Tanner Library, imported from the MOSIS website. 
  3.     .lib and .db files for the standard cell library, for use with Synopsys Design Compiler. 
The Tar file should be copied to the directory where your ICFB libraries reside, then extracted using 'tar -xvf msu_jennings_icfb.tar'. This will generate a library called 'tutorial' which contains the standard cells for ICFB, as well as a 'synopsys' directory containing the .lib and .db files for the standard cell library.
LEF Abstract File This is the LEF (Library Exchange Format) file used for Design Planner and Silicon Ensemble. This LEF file contains abstracts for all the cells contained in the Tar file.
Tar file containing 'tech' library  (1.5Mb) This library is used by some of the schematic views in the standard cell library.
topchip_nopads_se.mac This is the place-and-route script file for the Silicon Ensemble-only flow. It was previously not in the .tar file.

 

Tutorials

Standard_cell.ppt (2.03 Mb) Microsoft Powerpoint tutorial. A step-by-step guide to incorporating a new standard cell library into your Cadence design flow. 
Design_flow.ppt  (2.58 Mb) Microsoft Powerpoint tutorial. A step-by-step guide to utilizing an existing standard cell library in your Cadence design flow to generate a fully placed-and-routed design from a VHDL model..
Design_flow_pads.ppt (7.69 Mb)  Microsoft Powerpoint tutorial. A step-by-step guide to utilizing an existing standard cell library, with pads, in your Cadence design flow to generate a fully placed-and-routed design from a VHDL model.
Design_flow_se.ppt (3.72 Mb) Similar to Design_flow.ppt, but only uses Silicon Ensemble (no Design Planner steps) for the entire place-and-route process.

Tutorial Support Files

add_stdcells.tar (~29 Mb) Support files for Standard_cell.ppt. Use these files in conjunction with the Standard_cell.ppt tutorial. Copy the .tar file into an empty directory, then type 'tar -xvf add_stdcells.tar' to uncompress the files.
design_flow.tar (~21 Mb) Support files for Design_flow.ppt, Design_flow_pads.ppt and Design_flow_se.ppt. Use these files in conjunction with the those tutorials. 

Notes:

It is not recommended that you mix the standard_cell.ppt support files and the design_flow.ppt support files together. I have not tried to mix them together, so if you do, you might overwrite some files that are meant to be different.