The Static RAM Generator was designed for speed and ease in the modeling of Static RAMS of various address bus widths, data bus widths, and control functions.
Three files will be generated: an entity, an architecture, and a data file. File nomenclature for the entity is EntityName_.vhd, for the architecture is EntityName_ArchitectureName.vhd, and for the data file (if not specified) is EntityName_ArchitectureName.dat. If a data file is uploaded, it will be written out again to a file of the same name as the file that was submitted.
General Statement: All control signals (Output Enable, Write Enable, and Chip Enable) are assumed to be active HIGH. Also note that write-through functionality is not supported.
The following information includes explanations on all of the fields on the fill-out-form. Each field header on the form is linked to its corresponding section in this help document. The upper left-hand cell specifies whether a value is required or optional for that field. The lower left-hand cell specifies the default value, if any, when the field is left blank. The right-hand side gives a detailed explanation about the field, including information about the model returned from the generator.
|Required||Any alphanumeric name is permissable for an entity name. Restrict usage of punctuation, such as periods and underscores, which can interfere with interpretation of the nomenclature. |
The entity file name will be of the form
|Required||Only a behavioral architecture is available from the SRAM Generator. It is suggested that the architecture name reflect the behavioral level modeling of the SRAM. Suitable names are ones similar to behavioral, behavior, and bhv. Again, restrict usage of punctuation, such as periods and underscores, which can interfere with interpretation of the nomenclature. |
The architecture file name will be of the form
|Required||Any non-negative, non-zero integer value is allowed for the address width.|
The address bus signal name is a. It's associated wire delayed signal name is a_wd.
|Required||Any non-negative, non-zero integer value is allowed for the data width.|
The data bus signal name for the non-separate case is io. It's associated buffered signal name is io_buf.
The data input bus signal name for the separate case is di, and the output bus is do. The io_buf signal is the buffered input to the Memory Array.
|Optional||Output enable can be a function of itself and/or any other control signal, but must be a VHDL compilable logic function. |
When no value is assigned to the Output Enable Function, the signal is tied high.
|Optional||Write enable can be a function of itself and/or any other control signal, but must be a VHDL compilable logic function.|
When no value is assigned to the Write Enable Function, the signal is tied high.
|Optional||Multiple chip selects are supported by the SRAM generator. When configuring for more than one chip enable, suffix the ce signal with an integer number, eg. ce1, ce2, ce3, . . . .|
The chip enable function can be dependent upon the chip enable signal(s) and/or any other control signal, but must be a VHDL compilable logic function. Note when configuring for multiple chip enables, the selection of the chip will be controlled only by the evaluation of the Chip Enable Function.
|Required||Separate and non-separate I/O constructs are supported by the SRAM generator.|
Valid values are YES and NO.
|Default: YES (shared)|
|Required||If the X Generation variable is set to TRUE and a read timing violation is detected, no read is performed. For a write timing violation, when the X Generation variable is set to TRUE, a write is only performed when the violation was on a data set-up or hold time. An 'X' is written to the specified address due to an incomplete data valid time in such a case. When X Generation is FALSE, the read or write operation is performed regardless of timing violations on input signals.|
Valid values are TRUE and FALSE.
|Default: TRUE (on)|
|Required||If the Message Generation variable is set to TRUE and a timing violation is detected, an assertion message is generated explaining the timing violation. Otherwise, no violation message is written out.|
Valid values are TRUE and FALSE.
|Default: TRUE (on)|
|Required||Explanations of all timing parameters follow.|
|trc||Read Cycle Time (Stable Address Bus or Stable Active hip Enable)|
|taa||Address to Data Valid|
|toha||Data Hold from Address Change|
|tace||Chip Enable HIGH to Data Valid|
|tdoe||Output Enable HIGH to Data Valid|
|tlzoe||Output Enable HIGH to Low 'Z'|
|thzoe||Output Enable HIGH to High 'Z'|
|tlzce||Chip Enable HIGH to Low 'Z'|
|thzce||Chip Enable LOW to High 'Z'|
|twc||Write Cycle Time (taw + tha)|
|tsce||Chip Enable HIGH to Write End (CE or WE LOW)|
|taw||Address Set-Up to Write End (CE or WE LOW)|
|tha||Address Hold from Write End (CE or WE LOW)|
|tsa||Address Set-Up to Write Start (CE or WE HIGH)|
|tpwe||Write Enable Pulse Width|
|tsd||Data Set-Up to Write End (CE or WE LOW)|
|thd||Data Hold from Write End (CE or WE LOW)|
|tlzwe||Write Enable LOW to Low 'Z'|
|thzwe||Write Enable HIGH to High 'Z;|
|Optional||Instead of entering values in each of the fields in the fill-out-form, a data file containing the necessary information can be uploaded to the SRAM Generator site. When constructing a data file, consult the example data file for a list of variables and their proper format in the file. Note that there is no space between the ":" and the variable value, and that spaces are permitted within the variable value. In addition, the data file will be returned with the other SRAM files.|